Analogue to digital converter and method of analogue to digital conversion with non-uniform sampling

ABSTRACT

An analogue to digital converter generating at least two threshold levels and a comparator for comparing each of the levels with the input signal and generating a primary digital output signal to provide an indication that the input signal has crossed one of the threshold levels. The converter comprises a timer for determining the elapsed period of time between the input signal crossing a first level and the input signal crossing a second level and for generating a secondary output signal representing the elapsed time, whereby the secondary digital output signal and the corresponding primary output signal are used to provide a digital representation of the analogue input signal. The converter may also comprise a receiver of the primary digital output signal from the comparator and for providing an UP/DOWN digital output signal to indicate in which direction the input signal crossed the threshold level.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method and apparatus for converting ananalogue input signal into a digital representation. In particular, theinvention relates to an apparatus for providing a digital representationof an analogue signal having characteristics advantageous for waveformmatching and prediction.

2. Discussion of Prior Art

Analogue to Digital Converters (ADCs) enable an analogue input signal tobe converted into a digital representation of the input signal whichpreserves information contained in the input signal. In the simplest ADCform, the zero-crossing discriminator, the output changes from a logicalnaught to a logical one when the input voltage crosses a referencevoltage of zero volts. The input signal is transformed into ahard-limited telegraph function [D. Middleton and J. H. Van Vleck, IEEE,54, 1 (1966)]; a simple sequence of naughts and ones. The spectralinformation contained in the input signal is also contained in thetelegraph function, subject to a scaling factor, because the spectralinformation in the output digital representation is principally carriedin the time intervals between the zero-crossings.

More sophisticated ADCs comprise a number of threshold-crossingdiscriminators each with its own reference voltage, where adjacentreference voltages are spaced apart by a common amount. For example, theoutputs of sixteen discriminators expressed as a binary code wouldindicate that the input voltage lay somewhere between two particularreference voltages. However, for any significant amount of noise at theinput, the input signal cannot be considered static during theconversion processes, causing the output digital representation tochange rapidly and be almost indeterminate. To overcome this problem theinput signal is held constant using a “track and hold” circuit and theresulting unambiguous output digital representation during the “hold”phase is latched into a register by sample pulses which occur at equallyspaced intervals of time. At the same time, the output digitalrepresentation may be made more compact.

Analogue to digital conversion methods in which the input analoguesignal is periodically sampled at a predetermined constant rate and eachsampled value is converted into a corresponding digital representationare standard. To convert analogue signals having high frequencycomponents, a higher sampling rate must be used, resulting in anincreased amount of output digital information. Furthermore, the highsampling rate results in an increased amount of unnecessary digitalinformation for sections of the analogue input which have a relativelylow frequency. For analogue signals having both high and low frequencycomponents, a low sampling rate is not appropriate as the high frequencycomponents cannot then be correctly identified. Conventionally, thechoice of regular sampling rate is subject to the well known “Nyquistsampling criterion”.

Furthermore, constant sampling rate analogue to digital conversiontechniques are not particularly suitable for waveform matching and timeseries recognition applications. By sampling an analogue input amplitudeat a fixed rate, two similar signals evolving in two differenttimescales, such as a car engine running at two different speeds, willgive rise to two different output digital representations. Even thoughthe two signals originate from the same source, the two different outputdigital representations will not be recognised as such due to thedifferent timescales with which the input signals evolve.

In time series recognition applications, the analysis of data in thetime domain may be used to extract information from a single channelsensor. A time series may be used to construct a trajectory evolvingthrough multi-dimensional phase space which evolves with time over thesurface of a geometrical object. The comparison of one such geometricalobject, in particular a standard one, with a measured one provides acomparison of the state of one physical system with another. U.S. Pat.No. 5,835,682 describes a Heuristic processor which computes amulti-dimensional, nonlinear, predictive model constrained to predictthe next sample of the time series from which it was calculated. Theinput data to the Heuristic processor are digital representations ofanalogue source signals for which conventional uniform sampling rateADCs are employed. However, the use of uniform sampling rate analogue todigital converters has the inherent problem of introducing inaccuraciesin the comparison of the predicted to measured time series. Thisdegrades the temporal dependence and therefore has limitations when usedfor time series recognition applications.

The foundations of a general theory for randomised signal processing arediscussed by I. Bihnskis and A. Mikelsons in “Randomised SignalProcessing” (1992, Prentice Hall) which exemplifies the problems andbenefits associated with some methods for processing signals subjectedto non uniform sampling in time. The theory of non-uniform sampling forthe digital encoding of analogue sources has previously been proposed asa means for data compression [IEEE Transactions on Communications, Vol.COM-29, No.1, January 1981 pp.24-32]. In the scheme proposed in thispaper, information about an analogue source signal is contained in adigital representation of the time intervals between the crossing of theinput analogue signal and any of the number of fixed threshold levelsand in the direction of the threshold level crossing (up or down). Thescheme is disadvantageous in that the digital representation is notcompact and represents the interval between threshold crossings as pairsof zeros output at a regular rate. The pairs of zeros are interspersedwith a 2-digit binary code representing direction.

Another sampling technique for analogue to digital conversion isdescribed in IEEE Transactions on Circuits and Systems—II: Analogue andDigital Signal Processing, Vol. 43, No. 4, April 1996. In this case, thefinal aim of the technique is to generate samples of the input signalthat are uniformly spaced in time. This is done by recording the timeinstants at which the signal crosses any of the predetermined, fixed,quantisation levels, together with the specific quantisation levelinformation, thus forming an output sequence consisting of“amplitude-time” ordered pairs. This forms a local reconstruction of thesignal which is then re-sampled by interpolation to provide equalinterval amplitude samples. Once again, a non-compact sequence ofordered pairs is used to represent the input signal.

U.S. Pat. No. 4,291,299 describes a non-uniform sampling analogue todigital converter for converting analogue signals with large, short-termamplitude excursions. Such signals typically occur on telephone linesaffected by lightning strikes or from power system faults. The samplingis non-uniform in both time and amplitude. Before the signal is sampled,multiple predetermined, absolute voltage levels are set as thresholdlevels. The system samples an input analogue signal and, whenever theinput signal or the difference signal between the analogue signal andits last preceding sample, crosses any of the multiple predeterminedlevels this is detected and a digital code representing the particularlevel crossed is output This digital code forms part of an outputdigital word which also comprises a timer circuit count representing thetime which has elapsed since the preceding sample occurred

An alternative analogue to digital converter system is described by R.Greenhalgh (IBM Technical disclosure bulletin, Vol. 7, no. 9, February1965 (1965-02)). This document describes a system in which thresholdlevels are set at A±(ΔA/2), where A is an analogue representation of thedigital value stored in a register. If the input signal crosses one ofthe thresholds the register is reset to the value of the threshold thathas been crossed, and a digital signal is output from the system whichcontains a digital representation of the value stored in the registerand a digital representation of the absolute time value of the clock.Alternatively, the direction of the change in amplitude, as indicated bythe tick register, is recorded instead of the absolute voltage.

GB2179516 is concerned with sampling an analogue waveform at a frequencysignificantly greater than the Nyquist frequency. Simple averaging ofsuch an oversampled waveform to produce a waveform at the requiredsampling rate increases the dynamic range of A-D conversion. However,the method of GB 2179516 increases the dynamic range further bydescribing the analogue waveform as a mathematical function, from whicha digital representation can be output at a desired sampling rate.

It is an object of the present invention to provide a method andapparatus for converting an analogue input signal into a digitalrepresentation which overcomes the problems arising from the temporaldependence inherent in constant sampling rate analogue to digitalconverters. It is a further object of the invention to provide atechnique and apparatus for analogue to digital conversion whichprovides an output digital representation in compact form from which theoriginal input analogue signal can be substantially reconstructed.

For the purpose of this specification, the term ‘analogue to digitalconverter’ shall be taken to mean a device for converting an analoguesignal into a digital representation by sampling the input signal at asubstantially constant rate. The term ‘analogue to digital intervalconverter’ shall be taken to mean a device for converting an analoguesignal into a digital representation by sampling the input signal atsubstantially equal changes in amplitude. The term ‘time series’ shallbe taken to refer to a sequence of amplitude values generated as aresult of sampling an analogue input signal converted with smalluncertainties in amplitude, as in a conventional ADC. The term ‘timesequence’ shall be taken to refer to a sequence of time interval valuesgenerated as a result of sampling an analogue input signal convertedwith small uncertainties in time interval.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, an analogue to digitalconverter for converting an analogue input signal into a digitalrepresentation includes;

generation means for generating at least two threshold levels forcomparison with the analogue input signal,

comparison means for comparing each of the threshold levels with theinput signal and for generating a primary digital output signal toprovide an indication that the input signal has crossed one of thethreshold levels,

timing means,

characterised in that,

the elapsed period of time between the input signal crossing a firstthreshold level and the input signal crossing a second threshold levelat a later time is determined by the timing means and a secondarydigital output signal representing the elapsed period of time is alsogenerated by the timing means,

the secondary digital output signal and the corresponding primarydigital output signal being used to provide a digital representation ofthe analogue input signal.

In a preferred embodiment, the converter also comprises means forreceiving the primary digital output signal from the comparison meansand for providing an UP/DOWN digital output signal to indicate in whichdirection, UP or DOWN, the input signal crossed the threshold level,whereby the secondary digital output signals and the associated UP/DOWNdigital output signal constitute a digital representation of theanalogue input signal.

This provides the advantage that the output from the converter is seriesof signed, time interval values i.e. a digital representation comprisinga series a time interval values having an UP or DOWN (+ or −) signattached. The output from the converter can therefore be made compact.This is particularly advantageous for input signals which vary slowlywith time. Using a conventional analogue to digital converter, whichsamples at a constant rate, results in a large amount of output data asthe low frequency portions of the input signal are oversampled Thepresent invention alleviates this problem as the sampling rate isdetermined by the local rate of change of the input signal.

Conveniently, the digital representation may be expressed as a 2'scomplement number for subsequent input to a computer.

In addition, the analogue to digital interval conversion techniquesproposed in the prior art provide a non-compact data output. The presentinvention is advantageous in that the digital output signal is a compactsequence of time interval values having an UP or DOWN flag attached (+or −) to indicate the direction of threshold level change for a giventime interval.

The comparison means may comprise means for comparing each of thethreshold levels with the input signal or, alternatively, means forcomparing each of the threshold levels with a signal derived from theinput signal.

In a further preferred embodiment, the generation means includeadjustment means for adjusting the threshold levels relative to theinput signal in response to a threshold level crossing. This providesthe advantage that only two threshold levels need be used as they can bemade to track the input signal as it evolves in time.

In one embodiment of the invention, the adjustment means may comprisemeans for adjusting the threshold levels themselves in response to athreshold level crossing.

In this embodiment, the comparison means may comprise two comparators,each receiving the input signal and a different one of two thresholdlevels, UPPER or LOWER, forming an amplitude window about the currentinput signal, whereby if the input signal crosses one of the thresholdlevels the corresponding comparator generates a primary digital outputsignal to a subsequent logic stage for generating the UP/DOWN digitaloutput signal.

In addition, the generation means may comprise two digital to analogue,each for generating a different one of the two threshold levels, UPPERor LOWER, for input to the associated comparator, whereby the digital toanalogue converters each receive a digital input determined by thedirection of the UP/DOWN digital output signal generated by thepreceding threshold level crossing.

The digital to analogue converters may receive the digital inputs viacounter means which serve to increasingly or decreasingly adjust thethreshold levels accordingly in response to the UP/DOWN digital outputsignal generated by the preceding threshold level crossing.

Alternatively, the digital to analogue converters may receive thedigital inputs from a logic circuit which serves to increasingly ordecreasingly adjust the threshold levels accordingly in response to theUP/DOWN digital output signal generated by the preceding threshold levelcrossing.

Preferably, following each threshold crossing, the threshold levels aresubstantially equal to V_(REF)+ΔV and V_(REF)−ΔV, where V_(REF) is thevalue of the analogue input signal as the threshold level crossingoccurs and ΔV is a pre-set threshold voltage.

Alternatively, instead of adjusting the threshold levels themselves, thesignal derived from the input signal may be adjusted in response to thederived signal crossing a threshold level.

For example, the converter may comprise,

sample and hold means for sampling the analogue input signal to providea sample input value,

whereby the sample and hold means hold the sample input value until suchtime as the analogue input signal crosses one of the two, fixedthreshold levels, +ΔV or −ΔV, at which time the sample input value isadjusted, thereby adjusting the threshold levels relative to the inputsignal.

In this embodiment, the converter may comprise;

a differential amplifier, receiving at one input the sample input valueand receiving at the other input the evolving analogue input signal, thedifferential amplifier providing an output signal derived from the inputsignal, and

two comparators for comparing each of two, fixed threshold levels, +ΔV,−ΔV, with the derived signal and for providing the primary digitaloutput signal to provide an indication that the derived signal, andtherefore the input signal, has crossed a threshold level.

The converter may further comprise;

an absolute level crossing detection means, whereby the absolute-levelcrossing detection means provide an output each time the analogue inputsignal crosses the absolute level, and

means for adjusting the threshold levels relative to the analogue inputsignal in response to the absolute-level crossing detection output so asto correct for any cumulative errors in the threshold levels asrequired.

This provides the advantage that any cumulative errors in the adjustedthreshold levels or in the adjusted value of the input signal can becorrected for.

In one embodiment, the threshold levels themselves may be adjusted inresponse to the absolute-level crossing detection output. Alternatively,the analogue input signal may be adjusted in response to theabsolute-level crossing detection output. Typically, the absolute-levelcrossing detection means may be a zero-crossing detection means.

In an alternative embodiment of the invention, the converter maycomprise a flash analogue to digital converter for generating aplurality of fixed, digital threshold levels and for converting theanalogue input signal into a binary coded digital output, and whereinthe comparison means comprise logic circuitry for comparing the currentbinary coded digital output with the previous binary coded digitaloutput to determine whether and in which direction a threshold levelcrossing occurred. Typically, the logic circuitry compares at least thetwo least significant bits of the binary coded digital output with atleast the two least significant bits of the previous binary codeddigital output to determine whether and in which direction a thresholdlevel crossing occurred.

The timing means may comprise a timer counter for measuring the elapsedperiod of time which occurs between threshold level crossings. The timercounter may comprise means for determining when the maximum count hasoccurred.

In any of the embodiments of the invention, the converter may alsocomprise means for initially normalising the analogue input signal suchthat any two or more analogue input signals input to the converter havea common amplitude scaling. This is particularly advantageous forwaveform matching or time series recognition applications.

The converter may also comprise an anti-aliasing filter which serves tolimit the fastest rate of change of the analogue input signal so thatthe time interval to which the fastest rate of change corresponds isgreater than the time the converter takes to provide an output digitalrepresentation following a threshold level crossing.

According to a second aspect of the invention, a nonlinear systemanalyser for analysing an analogue input signal is characterised in thatit comprises;

the analogue to digital converter as herein before described, forgenerating a digital representation of the input analogue signal,

processing means for receiving said digital representation and forgenerating a multi dimensional nonlinear predictive model, wherein themodel is constrained such that it predicts the subsequent input signal.

The non linear system analyser may also comprise means for comparing thepredicted sample input signal with the measured input signal.

According to third aspect of the invention, a method of converting ananalogue input signal into a digital representation comprises the stepsof;

(i) generating at least two threshold levels (UPPER, LOWER),

(ii) comparing the at least two threshold levels with the input signal,

(iii) generating a primary digital output signal to provide anindication that the input signal has crossed one of the thresholdlevels,

characterised in that it comprises the additional steps of,

determining the elapsed period of time between the input signal crossinga first threshold level and the input signal crossing a second thresholdlevel at a later time,

producing a secondary digital output signal representing the elapsedperiod of time between the input signal crossing a first threshold leveland the input signal crossing a second threshold level at a later time,and

providing a digital representation of the input signal from thesecondary digital output signal and the corresponding primary digitaloutput signal.

The method may comprise the further steps of;

providing a single UP/DOWN digital output signal from the primarydigital output signal to indicate in which direction, UP or DOWN, theinput signal crossed the threshold level, and

providing a digital representation of the input signal comprising thesecondary digital output signals and the associated UP/DOWN digitaloutput signal.

The method may further comprise the step of expressing the digitalrepresentation as a 2's complement number. This provides the advantagethat for subsequent computer processing.

The method may comprise the further step of adjusting the thresholdlevels relative to the input signal in response to a threshold levelcrossing.

The method may comprise the step of comparing the input signal with twothreshold levels. In this case, the method may comprise the step ofadjusting the threshold levels themselves in response to the inputsignal crossing a threshold level so as to adjust the threshold levelsrelative to the input signal.

Alternatively, a signal derived from the input signal may be comparedwith the threshold levels. In this case, the method may comprise thestep of adjusting the derived signal in response to the derived signalcrossing a threshold level so as to adjust the threshold levels relativeto the derived signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described, by example only, with reference tothe following figures in which;

FIG. 1 illustrates a conventional analogue to digital sampling processin which the signal is sample at fixed time intervals,

FIGS. 2(a) and 2(b) illustrate the temporally independent samplingprocess of the present invention,

FIG. 3 shows a block diagram to illustrate the basic signal flow (STAGES1 to 4) of the invention,

FIG. 4 shows a block diagram of a signal input conditioning circuit(STAGE 1) which may be used in the invention,

FIG. 5 shows a feedback circuit which may be used to implement signalcomparison and level change detection (STAGE 2),

FIGS. 6(a) and (b) show alternative circuitry which may be used toimplement signal comparison and level change detection (STAGE 2),

FIGS. 7(a)-(f) illustrate the variation of the UPPER and LOWER thresholdlevels as the input signal varies over time for the circuit shown inFIG. 6,

FIG. 8 shows an alternative circuit which may be used to implementsignal comparison and level change detection (STAGE 2), comprising aflash analogue to digital converter,

FIG. 9(a) illustrates the principle of operation of a flash ADCconverter (as shown in FIG. 8), and FIG. 9(b) shows a table to indicatehow the level crossing direction can determined from the flash ADCoutput,

FIG. 10 shows a diagram of the logic circuitry (STAGE 3) which may beused for the level change detection in FIG. 8,

FIG. 11 shows an alternative circuit which may be used to implementsignal comparison and level change detection (STAGE 2), comprising aSample and Hold,

FIG. 12 shows a diagram of the timing circuit (STAGE 4) which may beused in the invention,

FIG. 13 shows a block diagram of a playback device which may be used toreconstitute the original input analogue signal and

FIG. 14 shows a schematic diagram to illustrate a nonlinear systemanalyser, including an analogue to digital interval converter.

DETAILED DESCRIPTION OF EMBODIMENTS

In a conventional Analogue to Digital Converter (ADC), the inputanalogue signal is sampled at a fixed rate and samples are thenconverted to give a digital representation of the original signal. Thissampling process is illustrated in FIG. 1. To convert analogue signalshaving high frequency components, a relatively short sampling period,Δt, must therefore be used. However, this results in an increased rateof output digital code. Furthermore, the high sampling rate results inan increased amount of unnecessary digital code for sections of theanalogue input which have a relatively low frequency. For input analoguesignals having both high and low frequency sections, a fixed samplingrate is not ideal as high frequency components may be lost or distortedby a lower frequency sampling rate whereas, for a higher frequencysampling rate, the low frequency components are oversampled.Conventionally, if the highest frequency component of an analogue signalis not known, the sampling frequency is determined by a band limitingfilter applied to the input and the sampling frequency must be at leasttwice the bandwidth of this filter.

In the present invention, instead of making a fixed choice by using aregular sampling rate the past history and current evolution in time ofthe input signal is used to determine the “correct” time at which thenext sample is taken. This process may be referred to as adaptive signalsampling.

The principle behind the analogue to digital conversion method of thepresent invention is illustrated in FIGS. 2(a) and 2(b) which shows aninput analogue waveform 10 evolving with time. A pair of dynamic UPPERand LOWER threshold values form an amplitude “window” about the currentinput analogue signal at a level REF. Referring to FIG. 2(a), time A isthe time at which the input signal 10 has the value REF and time B isthe later time at which the input signal 10 crosses the UPPER thresholdlevel. When the input signal 10 crosses the UPPER threshold level (timeB) a counter, counting clock pulses to measure a time interval, is resetand starts to count. The UPPER and LOWER threshold levels are moved to“track” the input signal 10, as will be described later, to new levels,as shown in FIG. 2(b), which form a window about the new value of theinput signal (i.e. REF in FIG. 2(b)).

The system records the time interval between the input signal waveform10 crossing the UPPER threshold level in FIG. 2(a) (time B) and crossingthe UPPER threshold level in FIG. 2(b) (time C). The system also recordsthe fact that the input signal 10 went UP one level, UP corresponding tothe UPPER level being crossed. The UPPER and LOWER threshold levels arethen moved to centre around a new reference level at time C and theprocess is repeated.

The output data set is therefore a combination of time intervals with UPor DOWN flags i.e. sign and magnitude representations. For computationalconvenience, this output may then be expressed as a 2's complementnumber for subsequent input to a computer.

The method of the invention operates in a different way to aconventional ADC in which the input signal is sampled at regularintervals in time and where the output consists of digital levels atfixed time intervals apart. For the purpose of this specification ananalogue to digital converter which does not sample an input signal atfixed intervals in time, but whose output comprises a sequence of timeinterval values representing the time intervals between adjacentthreshold level crossings shall be referred to as an Analogue to DigitalInterval Converter (ADIC).

A primary advantage of the invention is that the sampling rate isdetermined by the rate of change of the input signal, and not by animposed sampling time as in a conventional ADC. In the presentinvention, the dependence of signal sampling on absolute time istherefore removed. This makes the system particularly suitable forwaveform matching applications. For example, an engine running at twodifferent speeds will provide two signals evolving with differenttimescales. If the two different signals are input to the ADIC, theoutputs are time sequences which can be normalised and therefore, whencompared, will be recognised as a match.

FIG. 3 shows a block diagram of the ADIC and analogue to digitalinterval conversion method of the present invention. STAGE 1 is thesignal input and conditioning circuit, STAGE 2 is the signal comparisonand level change detection circuit, STAGE 3 is the threshold transitionand direction logic circuit, which feeds back to the previous stage(STAGE 2) to reset the UPPER and LOWER threshold limits, and STAGE 4 isthe timer circuit for generating the digital representation of theinter-level time intervals.

At STAGE 1 amplitude normalisation of the input analogue signal may takeplace in an attempt to ensure that all signals which are processed havea common amplitude distribution. This is essential if the digital outputfrom the ADIC is to be ultimately compared with digital outputscorresponding to other analogue signals, for example, in waveformmatching or time series recognition applications.

By way of background, if a conventional ADC is to be used to its bestadvantage the maximum input voltage excursion should have a peak-peakvalue which explores all the possible binary codes the ADC can provide.This means that the peak-peak input signal approaches the maximumspecified peak-to-peak input voltage for the ADC, V_(fs). For example,an ADC converts a positive-full-scale analogue input voltage to a binaryrepresentation of 01111111 for an 8 bit 2's complement binary codedconverter. Negative-full-scale is converted to 10000000. At half thepositive-full-scale analogue input voltage the code is 00111111 and11000000 for the negative. Therefore, to use the full resolution (allthe bits) of the converter the maximum input voltage excursion must begreater than V_(fs)/2 and less than V_(fs). Larger inputs than this willcreate an output representation which is a “clipped” version of theinput, whereas smaller ones reduce the resolution with which the signalis represented and essentially waste the resolution capability of theconverter. In conventional sampling systems this is not considered to bea problem, although conversion of two input waveforms with differingamplitudes will have different binary representations each requiringnormalisation before they can be compared.

Similar constraints exist for the present invention in which the timetaken for the input signal to change by +/−ΔV is of interest. If theamplitude of the input signal changes then each converted time intervalwill be scaled accordingly; ultimately to such an extent that there willbe a different number of time intervals representing the signal. Thissituation will degrade the waveform matching ability of the conversionprocess.

If two waveforms are to be compared they should be applied to theconverter with a common amplitude scaling. Automatic gain control (AGC)is a well known solution to this type of problem; the amplifier gain,however, has to be controlled on the basis of a common characteristic ofthe signals which varies with their amplitude. This characteristic willdepend on the use made of the digital output of the converter. The inputamplifier to the ADC has its gain controlled by a voltage calculatedusing the output voltage that is passed to the ADC. The relationshipbetween this voltage and the control voltage can be established as theresult of an arithmetic calculation. The input amplifier to the ADC hasits gain controlled by the measured RMS power of the signal it passes tothe converter. The RMS power of the signal can be measured over sometime interval long compared to the maximum time interval encountered inthe signal conversion process.

Alternatively the gain of the input amplifier can be established as theresult of a nonlinear operation. The input amplifier to the ADC has itsgain controlled by the excess of the modulus of the signal amplitudeover a set threshold. This can be determined over a given time period oraccumulated as a progressively increasing value. Derivations of theseand other useful characteristics of a signal are well known to thoseskilled in the art.

A block diagram of such an arrangement is shown in FIG. 4.

The arrangement shown in FIG. 4 comprises a voltage controlled amplifier12 (VCA) into which the input signal 10 (V(t)) is input. The voltagecontrolled amplifier 12 has a gain function G_(τ)(t) determined by acontrol voltage 11 (V_(c)(t)) calculated by the function calculationblock 16 (FCB) over a time τ. The control voltage 11 sets the gain ofthe VCA 12 generating a conditioned voltage 14 (V^(!)(t)).

G_(τ)(t) is given by the relationship;${{G_{r}(t)} = {G_{0} + {G_{m}( \frac{1}{1 + {V_{c}(t)}} )}}},$

 G _(τ)(t)=kV _(c)(t)

Where G₀+G_(m) is the maximum gain of the VCA for no input signal, V(t),(i.e. V_(c)(t)→0, G_(τ)(t)→G₀+G_(m)), and G₀ is the minimum gain of theVCA (i.e. V_(c)(t)→∞, G_(τ)(t)→G₀) and k is a constant ofproportionality.

The output 14 from the VCA 12 is given by the following;

V ^(!)(t)=G _(τ)(t)V(t)

This output is fed back to the FCB that calculates functionalrelationship between V_(c)(t) and V^(!)(t) over a time interval τ,V_(c)(t)=F(V⁴⁹ (t),τ).

If the chosen characteristic is the RMS signal power then${{{F( {{V^{!}(t)},\tau} )} \cdot} = \sqrt{\frac{\int_{\tau}{{V^{!}(t)}^{2}\quad {t}}}{\iota}}},$

If the chosen characteristic is the excess over a set voltage V_(max) ofthe modulus of the peak signal amplitude then

F(V ^(!)(t), τ).=Largest[(|V ^(!)(t)|−V _(max))>0]

The voltage V_(c)(t) is input to the VCA 12 to control the gain. Thenormalised output from the VCA 12 is passed to STAGE 2 of the ADIC.

STAGE 1 of the ADIC may also include an anti-aliasing filter for theinput signal 10. Conveniently, the anti-aliasing filter may be includedin the VCA. The anti-aliasing filter serves to limit the fastest rate ofchange of the input signal so that the time interval to which itcorresponds is greater than the time the ADIC takes to convert. Theconstruction of an anti-aliasing filter would be familiar to one skilledin the art.

At STAGE 2 the input analogue signal 10 is compared with the levels setby the preceding threshold crossing and, by this means, the change inlevel is detected. This may be implemented in several ways, as describedbelow. Embodiment 1 relates to a dual-DAC embodiment which makes use ofa counter, Embodiment 2 relates to an alternative dual-DAC embodimentwhich makes use of an adder and subtracter, Embodiment 3 relates to aflash ADC embodiment, and Embodiment 4 makes use of a sample and holdfunction. The particular application for which the ADIC is required willinfluence which of the embodiments is most preferable.

STAGE 2 Embodiment 1

FIG. 5 shows a feed back circuit comprising two comparators 20,22, twoDigital to Analogue Converters (DACs) 24,26 and an UP/DOWN counter 28.The normalised and band limited input signal 10 is fed into one input ofeach of the two comparators 20,22. The circuit also comprises an adder30 and subtracter 32 in the path between the UP/DOWN counter 28 and theDACs 24 and 26 respectively. The adder 30 adds one count to the counteroutput and the subtracter 32 subtracts one count from the counteroutput. Therefore, initially, one of the inputs to comparator 20 isV_(REF)+ΔV and one of the inputs to comparator 22 is V_(REF)−ΔV, whereΔV is the threshold voltage corresponding to 1 count and V_(REF) is thecurrent value of the input signal. In other words, the UPPER thresholdis set by DAC 24 and comparator 20 and is ΔV higher than V_(REF) and aLOWER threshold is set by DAC 26 and comparator 22 and is ΔV lower thanV_(REF). The UPPER and LOWER threshold levels therefore form a “window”about the current value of the input signal.

Using this arrangement, one of the comparators (comparator 20) comparesthe input signal 10 with an UPPER threshold level and the other(comparator 22) compares the input signal with a LOWER threshold level.The comparators 20,22 therefore serve to determine whether the inputsignal 10 is “increasing” or “decreasing” by comparing the current valueof the input signal with the UPPER and LOWER threshold levels. This isachieved as follows. As the input signal evolves, it will become equalto either the UPPER or LOWER threshold value (+/−ΔV). This causes thecorresponding comparator (20 or 22) to provide a digital output which isfed into STAGE 3 (details not shown in FIG. 5). The threshold (UPPER orLOWER) which has been crossed is determined and the appropriate UP orDOWN signal is generated in STAGE 3. The UP/DOWN signal generated inSTAGE 3 forms part of the ADIC output along with the time intervalbetween the current threshold transition and the previous one (to bedescribed later). This UP/DOWN signal from STAGE 3 is also fed back fromSTAGE 3 into the UP/DOWN counter 28 to increase or decrease the countaccordingly. This subsequently adjusts the count input to the DACs 24,26and therefore the comparator inputs are shifted, up or down on eitherside of the input signal, depending on whether the input signal hasincreased or decreased.

In summary, each time the input signal 10 crosses either the UPPER orLOWER threshold level, the following sequence of events occurs; theoutput from the comparator (20 or 22) triggers the subsequent thresholdtransition and level change direction logic (STAGE 3) to determine whichof the threshold levels was crossed and in which direction (UP or DOWN)the transition occurred. The UPPER and LOWER threshold levels are thenreadjusted, to establish a window around a new reference level, and thegeneration of a time interval at STAGE 4 is initiated.

Several different arrangements of the adder 30 and subtracter 32 may beused. For example, in practice, the subtraction of one count may be moreeasily implemented by adding a negative count. Alternatively, an adderor subtracter may be included in only one of the paths to the DACs, withthe other DAC receiving the count directly from the counter 28. However,the arrangement described above with reference to FIG. 5 is preferred asit avoids problems associated with noise which arise if the last inputvalue is one of the threshold levels, as in the single adder (orsubtracter) case. Furthermore, by including an adder or subtractercomponent in the paths between the UP/DOWN counter 28 and both of theDACs 24,26, no differential time delay is introduced between the twosignal paths.

In this embodiment of the invention (Embodiment 1), adjustment of thethreshold levels is limited to +/−ΔV in all circumstances because theUP/DOWN counter 28 counts up or down by +/−1 following a threshold levelcrossing. For example, consider the case where the UPPER threshold is+2ΔV and the LOWER threshold is −2ΔV. If the UPPER threshold level iscrossed by the input signal the counter will increase the thresholds by+1ΔV. The UPPER threshold therefore goes to +3ΔV and the LOWER thresholdgoes to −1ΔV and so the threshold levels do not form a symmetric windowabout the input signal. However, depending on the nature of the inputsignal to be converted to digital form, it may be useful to be able tochange the pre-set value of threshold voltage level. For example, if aninput signal has a large degree of noise fluctuation, a small thresholdvalue (such as ΔV) will cause an unnecessarily large number of leveltransitions to be registered, thus producing a larger data output streamthan is necessary to determine the general trend of the input waveform.Embodiment 1 is limited in this respect. This limitation may be overcomeusing the alternative embodiment of STAGE 2 of the invention (Embodiment2), as described below.

STAGE 2 Embodiment 2

An alternative circuit (Embodiment 2) for implementing STAGE 2 is shownin FIGS. 6(a) and 6(b). Embodiment 2 operates to vary upper and lowerthreshold levels so as to maintain the amplitude of the input signalbetween them, as described previously for Embodiment 1. This embodimentprovides the further advantage over Embodiment 1 that the thresholdvoltages can be selected to be any number of DAC levels. For practicalreasons, the selected threshold value must not be excessive to enablethe DAC levels to change for an increase or decrease in the inputsignal. In this embodiment, problems arising due to noise fluctuationson a signal which would otherwise result in an UPPER or LOWER thresholdlevel being crossed can be avoided by increasing the magnitude of thethreshold voltage.

Referring to FIG. 6(a), the circuit comprises a buffer 40 which buffersthe input signal 10. The buffer 40 outputs the input signal 10 to twocomparators 42,44. The two comparators 42,44 also receive the value ofthe UPPER and LOWER threshold levels from outputs 46 and 48 from DACs 50and 52 respectively. The comparators 42,44 therefore serve to determinewhether the input signal is “increasing” or “decreasing” by comparingthe current input sample with the UPPER and LOWER threshold levels, asfor Embodiment 1.

The outputs from comparators 42,44 are passed to a control logic circuit54 (shown in detail in FIG. 6(b)), where new values of the UPPER andLOWER threshold levels are set. If the UPPER threshold is crossed,comparator 42 provides an output UP signal, 90 a, to the control logiccircuit and if the LOWER threshold is crossed comparator 44 provides anoutput DOWN signal, 90 b, to the control logic circuit 54.

Referring to FIG. 6(b), the UP/DOWN outputs 90 a, 90 b from comparators42,44 (as shown in FIG. 6(a)) are input to logic means 77, to derive asingle output signal 60 having a value of 0 or 1 (0 to indicate DOWN, 1to indicate UP) to initiate the appropriate change in the thresholdlevels, as described below. Outputs 56, 58 from the control logiccircuit 54 then provide the new UPPER and LOWER threshold levels to DACs50,52.

The elements of the control logic circuit 54 include an adder 70 and asubtracter 72. A threshold value. 74 (“THRESHOLD”) is input to the adder70 and subtracter 72 by the user. The adder and subtracter serve tocalculate values of the UPPER and LOWER threshold levels respectivelyfrom the THRESHOLD and a reference value (“REFERENCE”) which is storedin a storage register 76 and has the value of the preceding inputsignal. The UPPER threshold value is equal to REFERENCE plus THRESHOLDand the LOWER threshold value is equal to REFERENCE minus THRESHOLD.

The circuit 54 also comprises a multiplexor 78. The UP or DOWN signal60, derived from one or other of the comparators 42,44, is input to themultiplexor 78 which selects data for transfer through the multiplexordepending on the direction of change in amplitude of the input signal10; the data on busses 80 and 82 at this time are static and are equalto the last REFERENCE value latched by register 76 plus or minus theTHRESHOLD value. Output storage registers 84,86 store the UPPER andLOWER threshold values respectively for subsequent input to the DACs50,52, and thus for subsequent input back to the comparators 42,44.

The UP/DOWN signal 60 (i.e. that signal provided to the multiplexor 78to initiate selection of one or the other of the UPPER or LOWERthreshold values) also forms part of the ADIC output. The ADIC outputalso comprises a time interval signal which is the time interval betweenthe preceding and the present threshold level transition. The timeinterval is deduced at STAGE 4 of the ADIC.

When the mulitplexor output is static the data is latched by register 76and becomes the new value of the REFERENCE bus 75. Data on the REFERENCEbus 75 and the value of the THRESHOLD are then used to calculate newvalues for the UPPER and LOWER busses 80,82 by the adder 70 andsubtracter 72 respectively. During the period of these changes thevalues input to the DACs 50,52 are maintained by registers 84,86respectively. The cycle is completed by clocking registers 84,86 tolatch the new UPPER and LOWER threshold levels for conversion by theexternal DACs 50,52. The DAC outputs 46,48 provide equivalent analoguethresholds which lie above and below the current amplitude of the inputsignal (subject to bandwidth considerations). The process is organisedby a sequence of clock signals (not shown in FIGS. 6(a) and 6 (b)) andthe circuit is left with static data on the UPPER bus 80 and the LOWERbus 82 ready for the next cycle start.

In order to understand the general principle of operation of Embodiment2 it is also helpful to consider how the UPPER and LOWER thresholdvalues change over time. These changes are depicted in FIG. 7; (a)-(e)show a sequence of events in time and (f) shows the locus delineated bythis sequence. The input signal waveform is referred to generally as 10.Referring to FIG. 7(a), at time t1 the input signal 10 is equal toREFERENCE and the UPPER and LOWER threshold levels (i.e. the DAC levels)respectively have values equal to the REFERENCE value plus or minus athreshold value (ΔV). The threshold value (ΔV) can be determined by theuser. As in the embodiment shown, it is preferable to add and subtractthe same threshold value (ΔV) to the REFERENCE level to give UPPER andLOWER levels which are equidistant in magnitude from the REFERENCElevel. However, it is also possible to implement UPPER and LOWERthreshold levels which are not equidistant from the REFERENCE level.

At later time t2, the input signal has crossed the UPPER threshold leveli.e. REFERENCE has increased and has the value of the preceding UPPERthreshold. At this time, t2, both thresholds (UPPER and LOWER) are movedto their new, increased levels, as seen in FIG. 7(b). Therefore, for anincrease in the input signal 10 the effect is that the UPPER level (FIG.7(a)) is shifted upwards, as is the LOWER threshold level, to their new,increased levels (as shown in FIG. 7(b)) which are established about theREFERENCE level at the later time t2. The UPPER and LOWER thresholdlevels have therefore changed by the threshold value (ΔV) with theevolving input signal 10.

Moving on in time, at time t4 (FIG. 7(c)) the now decreasing inputsignal 10 crosses the LOWER threshold level i.e. the REFERENCE level hasdecreased and has the value of the preceding LOWER threshold. At thistime, t4, both threshold levels are moved to their new, decreasedlevels, as seen in FIG. 7(d). Therefore, for a decrease in the inputsignal the LOWER level is shifted downwards as is the UPPER level to newdecreased levels (FIG. 7(d)) established about the REFERENCE level atthe later time t4.

The process continues through FIGS. 7(d) to 7(e) as the input signal 10reaches time t6. FIG. 7(f) shows the time evolution of the UPPER,REFERENCE and LOWER levels (92,94 and 96 respectively) during thisperiod of evolution of the input signal.

It may be advantageous to employ an absolute level crossing detectionmeans in STAGE 3 to indicate that the input signal 10 has crossed anabsolute level, for example zero volts. The effect of the absolute levelcrossing detection signal is to reposition the REFERENCE, UPPER andLOWER levels at and about the known absolute value of the input voltage,thereby removing any cumulative errors which may have occurred in thethreshold levels. In this way, each time the input signal crosses zero,for example, the threshold levels are reset around zero. This isachieved by feeding back the zero crossing detection signal to STAGE 2.The absolute level crossing detection means and reset may also beincluded in the previous example shown in Embodiment 1.

STAGE 2 Embodiment 3

In another alternative embodiment (Embodiment 3), a flash analogue todigital converter (flash ADC) may be used to implement the signalcomparison and level change detection of STAGE 2 of the system. FIG. 8shows a circuit comprising a flash ADC 100 (STAGE 2) in combination withthe elements required for STAGE 3 of operation (i.e. thresholdtransition and direction logic). STAGE 3 comprises a level change logicsection 102 and a comparison logic section 104. The flash ADC 100comprises an array of threshold detectors having thresholds increasingby a common value, ΔV. The flash ADC 100 may be free running or may beclocked and samples the input analogue signal 10.

The output of the flash ADC 100 is decoded so that at least a two bitcode is available whose current value and the previous history of valuescan be used to determine the direction of and interval between thethreshold crossings at STAGE 3. Usually, the two bit code will be thetwo least significant bits (LSBs) of a binary coded output (BITs 0 and 1in FIG. 8). The digital output of the flash ADC 100 is then fed directlyto the level change logic section 102 and the comparison logic section104 to determine if either the UPPER or LOWER threshold level has beencrossed. This is done by comparing the current binary coded output withprevious binary coded outputs, or at least, by comparing the current thebinary coded output with the previous two adjacent binary coded outputs.

If a level change is detected, the comparison logic 104 determines inwhich direction the transition occurred by comparing the output from thelevel change logic with the 2 least significant bits of the two previousdecoded outputs from the flash ADC. It is necessary to store the mostrecent three output changes in order that the direction of motion can becorrectly obtained.

FIG. 9(a) illustrates how the flash ADC system works. The flash ADClevels are referred to as n, n+1, n+2, n+3. The level crossings areindicated by reference numeral 105. A level change will only be producedwhen the input signal has gone up or down a full quantisation level fromthe previous one. The input signal 10 shown in FIG. 9(a) starts at n,having come up from level n−1. The level it has crossed in doing so istherefore between n−1 and n. For the signal to go up one level it mustcross the level between n and n+1 and to go down it must cross the levelbetween n−1 and n−2. Therefore, when the signal 1 reaches the n+3 areain the figure, it can be seen that a level change should only occur whenthe signal reaches the level between n+2 and n+1.

FIG. 9(b) shows a table to illustrate how the two LSBs of the digitaloutput from the flash ADC are used to determine in which direction thelevel crossing occurred. The direction UP or DOWN is determined byconsidering the difference between the current BITS 0 and 1 and thepreceding BITs 0 and 1 (UP=+1, DOWN=−1). For the columns indicated“CHANGE OF SIGN” (corresponding to times t5 and t9), there has been nofull change in threshold, ΔV, since the last level crossing andtherefore there is no signed time interval output from the ADIC. Forexample, considering the earliest change of state (time t5), only whenthe input signal crosses level n+2 at time t6 is a threshold crossingregistered (DOWN) and then a time interval corresponding to t6−t4 willbe output.

FIG. 10 shows a possible implementation of the logic which may be usedto implement the level change detection of STAGE 3 (i.e. box 102, alsoshown in FIG. 8). The two least significant bits, BIT 0 and BIT 1, fromthe flash ADC 100 constantly provide two data bits to the comparisonlogic 104. The level change detection logic 102 comprises a two bitlevel store 106, a single bit data store 108 and amplitude changedetection logic 110. BIT 0 and BIT 1 are also passed to the two bit datastore 106 to hold their state at the last level change and a single bitlevel store 108 to hold the associated ‘1’ or ‘0’ value describingwhether the level change was an UP or DOWN (output 112). Therefore,there is a memory which indicates where the signal was last clocked(outputs 114) and a memory which remembers in which direction it moved.

As a result, the amplitude change detection logic 110 uses thisinformation to create values U_(HL) and D_(HL). The comparison logic 104then compares U_(HL) and D_(HL) with BITs 0 and 1. When the comparisonlogic 104 detects a match between BIT 0 and BIT 1 and either U_(HL) orD_(HL), signifying an UP or DOWN level change, a level change pulse 120is emitted with the relevant UP or DOWN output, 90 a or 90 b,respectively, clocked high. As described previously, the UP and DOWNoutputs may be coupled to give a single logic output (0=DOWN, 1=UP). Thetwo bit data stores may comprise edge triggered D-types and are clockedby the level change pulse 120.

As a result of the level change output 120 going high, the 2-bitregister clocks and shifts the relevant data across. The level changeoutput is then passed to a timer circuit (STAGE 4) to trigger a counterdevice. A zero or absolute level crossing detection means may also beincluded in the flash ADC embodiment of the invention, as describedpreviously.

STAGE 2 Embodiment 4

An alternative circuit (Embodiment 4) for implementing STAGE 2 is shownin FIG. 11. The circuit makes use of a sample and hold function at theinput. Only two threshold levels are required in this example, as inEmbodiments 1-3. However, in this case, the thresholds themselves arenot varied dynamically as the input signal evolves. Instead, means areprovided for adjusting a derivation of the input signal as it is appliedto two, fixed threshold levels. In this embodiment, the derived signalis compared with the threshold levels. The thresholds therefore appearto vary dynamically as the input signal evolves, even though they aremaintained at fixed levels. In each case, the effect of adjusting eitherthe threshold levels or the derived signal in response to a thresholdlevel crossing is to effectively reinstate a common threshold (e.g.+/−ΔV) between the input signal and each of the UPPER and LOWERthreshold levels following each threshold crossing. For the purpose ofthis specification the phrase “adjusting the threshold levels relativeto the input signal in response to the input signal crossing a thresholdlevel” shall be taken to mean either that the threshold levels areadjusted explicitly in response to the input signal crossing a thresholdlevel or that a derivation of the input signal is adjusted in responseto the derivation of the input signal crossing a threshold level (i.e.the threshold levels are implicitly adjusted).

The phrase “comparing the input signal with threshold levels” shall betaken to mean either that the input signal itself is compared withthreshold levels or that a derivation of the input signal is comparedwith threshold levels.

Referring to FIG. 11, the circuit comprises an input buffer 122 whichbuffers the input signal 10. From here the input signal is passed toboth a differential amplifier 124 and a sample and hold (S/H) 126 whichsamples the input signal and holds the value for a certain period untila threshold crossing occurs. The circuit also comprises two comparators128,130. The threshold level for one comparator (128) is +ΔV and thethreshold level for the other (130) is −ΔV, both threshold levelsremaining fixed at these values at all times. The outputs 132,134 fromthe comparators 128,130 are passed to the comparison and level changedetection logic of STAGE 3. As described previously, the output fromSTAGE 3 provides the ADIC output (a digital representation of signedtime intervals). The level change detection signal 120, to indicate thatone or other of the threshold levels, +/−ΔV, has been crossed, is alsofed back from STAGE 3 to the S/H 126.

Initially, the signal 10 is input, via a buffer 122, to one input of thedifferential amplifier 124. The other input is taken from the S/H 126which is assumed to be holding the same value as the input signal 10. Atthis time, the output 138 from the differential amplifier 124 istherefore zero. The S/H 126 holds this sampled value of the input signaland, if the input signal increases, the differential amplifier outputwill increase in a positive direction until the inputs received atcomparator 128 are eventually equal. When the input signal crosses thethreshold +ΔV the comparator 128 will trigger. The comparator output 132is passed to STAGE 3, to provide an indication to the thresholdtransition and direction logic that the upper threshold level (+ΔV) hasbeen crossed.

STAGE 3 outputs a signal 120 to indicate that a level has been crossedand this is fed back to the S/H 126 to sample the output from the buffer122 and thus reset the differential amplifier output to zero ready forthe next input signal sample. As before, the S/H holds the last value ofthe sampled input signal while the input signal continues to evolve,until the input signal again increases or decreases by an amount +/−ΔV,thereby crossing one of the threshold levels and causing the appropriatecomparator to change logic state. The sequence continues and each time acomparator triggers, to indicate a threshold has been crossed, thetiming circuitry is started and time intervals between level crossings,and the direction of the change of the level crossing, are output fromSTAGE 3 to form the output from the ADIC.

Due to the finite capacitance of the S/H, which causes slow “memoryloss” of the stored voltage, this embodiment may not be particularlysuitable for slowly evolving input signals as the input value may not beheld by the S/H for a sufficiently long enough time for the input signalto cross a threshold level +/−ΔV. The time constants associated with theS/H are selected depending on the particular application of the ADIC.For some application, such as for highly dynamic input signals, theEmbodiment 4 embodiment may have advantages.

STAGE 4

An example of the timing circuit which may be used is shown in the blockdiagram in FIG. 12. The circuit is responsible for generating signedtime intervals between threshold transitions. In each of the embodimentsof the ADIC described previously, the signals received by the timingcircuitry include the sequence of pulses from the STAGE 3, the timeinterval between each successive pulse being the required time intervalbetween threshold crossings, the direction (UP or DOWN) in which thelast level crossing occurred.

Referring to FIG. 12, the signed time intervals form the output from theADIC. A counter 140 is driven from a fixed rate oscillator 142. Thecount continues until a threshold is crossed, triggered by the levelchange output at STAGE 3, at which point the counter contents are movedto a register 144 and the counter 140 is reset and restarted. Thedirection of the transition (UP or DOWN), provided by the UP/DOWN signal60, is converted by the logic in STAGE 3 to a sign bit (UP or DOWN) 148which is combined with the register value to give a signed timeinterval. The signed time intervals stored in register 144 form thedigital representation output from the ADIC.

In addition, different embodiments of the invention may provideadditional signals to the timing circuitry of STAGE 4. For example,regarding Embodiments 1-3, a pulse indicating that the input signal hascrossed an absolute known voltage level, which may be set to zero volts,may also be provided to STAGE 4. A flag indicating the direction of theabsolute level crossing may also be passed to STAGE 4. In this way, theresetting of the threshold levels about the absolute voltage level doesnot result in the output of a timing interval (unless it corresponds toa genuine threshold level crossing). An additional signal may also bepassed to the timing circuitry to indicate the time interval for whichthe threshold crossing is operating in an indeterminate or erroneousstate.

One problem which may have to be addressed is the problem of the maximumcount. This occurs when the input signal does not cross a thresholdbefore the counter overflows. For example, the counter may be arrangedsuch that at maximum count it registers the overflow and resets, so thatthe total interval for the transition is the maximum count (or more thanone maximum count depending on the number of times the counteroverflows) plus an actual count. Each time the counter overflows themaximum count is shifted to a FIFO for input to the subsequentprocessing means and the counter is reset to start counting again fromzero. When a threshold crossing eventually occurs an UP/DOWN signal isreceived from STAGE 3, at which time the current count is added to themaximum count (or however many maximum counts have occurred since thelast threshold crossing) to determine the time interval between thecurrent threshold crossing and the preceding one. A problem may ariseif, during the finite time the counter takes to reset when an overflowoccurs, a threshold level crossing occurs. If encountered, this problemmay be avoided in a number of ways using conventional electronictechniques.

SIGNAL PLAYBACK

A playback device which may be used to reconstitute the sequence ofsampled amplitudes of the original analogue signal from the ADIC digitaloutput is shown in FIG. 13. The level change pulse 120 and the UP/DOWNsignal output 90 a, 90 b are input to an 8 bit counter 150. The 8 bitcounter 150 is an UP/DOWN counter, the level change pulse is delayedslightly to allow the correct UP/DOWN control to be applied and then thecounter 150 is clocked by the level change pulse. The value of thecounter 150 is constantly connected to an 8 bit Digital to Analogueconverter (DAC) 152 and the value apparent at the DAC output 154 is thereconstituted input signal. As with conventional sampling, theseamplitudes may be subjected to interpolation and fitting routines toproduce a smooth function of time. The advantage of the ADIC is that theamplitudes do not have the inter-level uncertainty of conventional ADCs.Instead the uncertainty is associated with the time intervals. However,time can be measured with much greater precision than amplitude.

APPLICATIONS OF THE ADIC

The ADIC of the invention may be used to provide a solution to the wellknown problem of offset correction across an array of detectors. Eachelement of the detector array may be input to an ADIC of the presentinvention. As described previously, the signed time intervals outputfrom the ADICs will correspond to the rate of change of the inputsignal. They will not correspond to the constant or slowly changingoffset. Each detector output signal can therefore be reconstructed fromthe ADICs outputs on a common offset across the array. By using an RMSsignal power controlled amplifier, it may also be possible to correctfor the detector gain as well.

The ADIC of the present invention provides an output which isadvantageous for applications of waveform matching and recognitionapplications, as the temporal dependence of the sampling technique isremoved. For two input waveforms obtained from the same physical system,such as a car engine running at two different speeds, the two digitalrepresentations obtained from the ADIC will be recognised as a match.This is not the case for conventional regular interval analogue todigital conversion.

The ADIC of the invention may be used at the input stage of a nonlinearsystem analyser which is used, in particular, for the analysis of datain the time domain. Data analysis in the time domain is used inpreference to frequency domain analysis using discrete Fourier spectraltechniques because the latter cannot provide adequate information aboutnonlinear relationships in the data points. Fourier spectral techniqueslinearly transform one set of data points into another providing aspectral estimation which contains no time sequential information.

FIG. 14 shows a schematic diagram of a non linear system analysercomprising the ADIC 160, as described herein. The input analogue signal10 from the physical system to be analysed 162, for example a carengine, is input to the ADIC 160 where it is converted to a digitallyequivalent representation, as previously described, for input to adigital processor. The processor 164 may be a Heuristic Processor, asdescribed in U.S. Pat. No. 5,835,682, which is designed to estimateunknown results by an empirical self-learning approach based on theknowledge of prior results. The digital output from the ADIC is in theform of signed magnitudes, but for the purpose of subsequent computerprocessing this digital output should be expressed as a 2's complementcode.

In a conventional nonlinear system analyser, the input signal, which isa continuous function of time, is sampled at regular intervals, using aconventional constant sampling rate analogue to digital converter. Thisresults in a sequence of values called a time series. The processor 164uses this time series to construct a trajectory evolving throughmulti-dimensional phase space whose axes are determined using a SingularValue Decomposition (SVD) calculation. The trajectory evolves with timeover the surface of a geometrical object, called an attractor, which isa characteristic representation of the state of the physical system 162from which the input signal 10 was generated. Each point on an attractorhas an associated coordinate vector with sufficient elements to positionit in a phase space with enough dimensions so that the trajectory doesnot intersect. Thus, a set of coordinate vectors is calculateddescribing points which uniquely represent a multi-dimensionalgeometrical object. Since attractors are characteristic of the physicalsystem which generated them, these geometrical objects provide a meansof comparing physical systems.

The comparison is achieved by calculating a multi-dimensional,nonlinear, predictive model of the trajectory which delineates thestandard attractor. This mathematical model is constrained to predictthe next sample in the time series from which it was calculated. In theprior art, when an input signal 10 is measured experimentally, and thetime series deduced, the coordinates of its reconstructed trajectory aresubmitted to this model which, within its ability to generalise fromdata supplied by the standard, predicts the value of the next timeseries sample. The difference between the model's estimate and theactual measured value indicates the similarity of the two time series.

The following references describe non-linear system analysis in which atime series is processed to achieve a trajectory reconstruction; R.Jones, D. S. Broomhead, 1989, “Phase spaces from experimental timeseries”, IEEE Conference on Electronic Circuits Theory and Design,Brighton, D. S. Broomhead and G. P. King, 1986, “Extracting qualitativedynamics from experimental data”, Physica 20D, pp 217-236, D. S.Broomhead, R. Jones, 1989, “Time series analysis”, Proc. Roy. Soc.London A 423, pp 103-121.

In known non linear systems analysers, a problem arises with thecomparison described above due to the temporal dependence of the timeseries input to the processor 164. This is because the temporalevolution of the trajectory has been intimately tied to the originalsample clock used to conventionally digitise the signal. Thus, if thesignal has a waveform which repeats and the digitising clock is changed,or the waveform is dilated in time, the resulting reconstructedtrajectory, although of similar “shape”, will evolve through the phasespace at a different rate and will not be temporally equivalent.Therefore, for input signals generated by the same physical system,having similar waveforms but having a different frequency (e.g. a carengine running at different speeds) the corresponding multi dimensionalgeometrical objects generated by the processor 164 will not beequivalent and the input signals will not be recognised as having arisenfrom the same waveform.

This problem is overcome by the apparatus of the invention, as shown inFIG. 14. In the ADIC 160, the input signal waveform 10 is sampled atirregular intervals and this results in a sequence of values (hereindefined as a time sequence) each of which has an associated UP or DOWNflag depending on whether the amplitude of the input is increasing ordecreasing respectively. This time sequence is input to the processor164 and is used by the processor to compute the trajectory which evolveswith time over the surface of the geometrical object. In this way, thetemporal evolutionary disparity in conventional non linear systemsanalysers is removed. In removing the temporal dependence from thesystem, the geometrical objects computed from input signal arising fromthe same physical system, but with a time dilated waveform, will beequivalent independent of their frequency dependence.

What is claimed is:
 1. An apparatus for converting an analogue inputsignal into a digital representation including; generation means forsimultaneously generating at least two different threshold levels forcomparison with the input signal, comparison means for comparing each ofthe threshold levels with the input signal and for generating a primarydigital output signal to provide an indication that the input signal hascrossed a threshold level, and timing means for determining any elapsedperiod of time between the input signal crossing a first threshold leveland the input signal crossing a second threshold level at a later timeand for providing a secondary digital output signal representing theelapsed period of time, wherein the secondary digital output signal andthe corresponding primary digital output signal providing a digitalrepresentation of the analogue input signal.
 2. The apparatus of claim1, and further comprising means for receiving the primary digital outputsignal from the comparison means and for providing an UP/DOWN digitaloutput signal to indicate in which direction, UP or DOWN, the inputsignal crossed the threshold level, whereby the secondary digital outputsignals and the associated UP/DOWN digital output signal constitute adigital representation of the analogue input signal.
 3. The apparatus ofclaim 1, wherein the generation means include adjustment means foradjusting the threshold levels relative to the input signal in responseto a threshold level crossing.
 4. The apparatus of claim 3, wherein theadjustment means comprise means for adjusting the threshold levelsthemselves in response to a threshold level crossing.
 5. The apparatusof claim 4 wherein the comparison means comprise two comparators, eachreceiving the input signal and a different one of two threshold levels,a threshold level greater than the input signal (UPPER) or thresholdlevel less than the input signal (LOWER), forming an amplitude windowabout the current input signal, whereby if the input signal crosses oneof the threshold levels the corresponding comparator generates a primarydigital output signal to a subsequent logic stage for generating theUP/DOWN digital output signal.
 6. The apparatus of claim 5, wherein thegeneration means comprise two digital to analogue converters, each forgenerating a different one of the two threshold levels, UPPER or LOWER,for input to the associated comparator, whereby the digital to analogueconverters each receive a digital input determined by the direction ofthe UP/DOWN digital output signal generated by the preceding thresholdlevel crossing.
 7. The apparatus of claim 6, wherein the digital toanalogue converters receive the digital inputs via counter means whichserve to increasingly or decreasingly adjust the threshold levelsaccordingly in response to the UP/DOWN digital output signal generatedby the preceding threshold level crossing.
 8. The apparatus of claim 6wherein the digital to analogue converters receive the digital inputsfrom a logic circuit which serves to increasingly or decreasingly adjustthe threshold levels accordingly in response to the UP/DOWN digitaloutput signal generated by the preceding threshold level crossing. 9.The apparatus of claim 3 wherein, following each threshold crossing, thethreshold levels are substantially equal to V_(REF)+ΔV and V_(REF)−ΔV,where V_(REF) is the value of the analogue input signal as the thresholdlevel crossing occurs and ΔV is a pre-set threshold voltage.
 10. Theapparatus of claim 3, and further comprising; an absolute level crossingdetection means, whereby the absolute-level crossing detection meansprovide an output each time the input analogue signal crosses theabsolute level, and means for adjusting the threshold levels relative tothe analogue input signal in response to the absolute-level crossingdetection output so as to correct for any cumulative errors in thethreshold levels.
 11. The apparatus of claim 10, wherein theabsolute-level crossing detection means is a zero-crossing detectionmeans.
 12. The apparatus of claim 10, wherein the threshold levelsthemselves are adjusted in response to the absolute-level crossingdetection output.
 13. The apparatus of claim 1, wherein the comparisonmeans comprise means for comparing each of the threshold levels with asignal derived from the input signal.
 14. The apparatus of claim 13comprising, sample and hold means for sampling the analogue input signalto provide a sample input value, and means of adjusting the sample inputvalue held by the sample and hold means, thereby adjusting the thresholdlevels relative to the input signal, when the analogue input signalcrosses one of the two threshold levels, +ΔV or −ΔV.
 15. The apparatusof claim 14, comprising; a differential amplifier, receiving at oneinput the sample input value and receiving at the other input theevolving analogue input signal, the differential amplifier providing anoutput signal derived from the input signal, and two comparators forcomparing each of two, fixed threshold levels, +ΔV, -ΔV, with thedifferential amplifier output and for providing the primary digitaloutput signal to provide an indication that the derived signal, andtherefore the input signal, has crossed a threshold level.
 16. Theapparatus of claim 1, wherein the generation means comprise a flashanalogue to digital converter for generating a plurality of fixed,digital threshold levels and for converting the analogue input signalinto a binary coded digital output, and wherein the comparison meanscomprise logic circuitry for comparing the current binary coded digitaloutput with the previous binary coded digital outputs to determine whenand in which direction a threshold level crossing occurred.
 17. Theapparatus of claim 16, wherein the logic circuitry compares at least thetwo least significant bits of the previous binary coded digital outputswith at least the two least significant bits of the previous binarycoded digital output to determine when and in which direction athreshold level crossing occurred.
 18. The apparatus of claim 1, whereinthe timing means comprises a timer counter for measuring the elapsedperiod of time which occurs between threshold level crossings.
 19. Theapparatus of claim 18, wherein the timer counter has a maximum count,and wherein the timing means further comprise means for determining whenthe maximum count has occurred.
 20. The apparatus of claim 1, andfurther comprising means for initially normalising the analogue inputsignal such that any two or more analogue signals input to the converterhave a common amplitude scaling.
 21. The apparatus of claim 1, and alsoincluding an anti-aliasing filter which serves to limit the fastest rateof change of the input signal so that the time interval to which thefastest rate of change corresponds is greater than the time theconverter takes to provide an output digital representation following athreshold level crossing.
 22. A nonlinear system analyser for analysingan analogue input signal, said analyser comprising: the apparatus ofclaim 1 for generating a digital representation of the input signal, andprocessing means for receiving said digital representation and forgenerating a multi dimensional nonlinear predictive model, wherein themodel is constrained such that it predicts the subsequent input signal.23. The non linear system analyser of claim 22, further including meansfor comparing the predicted sample input signal with the measured inputsignal.
 24. A method of converting an analogue input signal into adigital representation comprising the steps of; (i) generating at leasttwo threshold levels (UPPER, LOWER), (ii) comparing the at least twothreshold levels with the input signal, (iii) generating a primarydigital output signal to provide an indication that the input signal hascrossed one of the threshold levels, (iv) determining the elapsed periodof time between the input signal crossing a first threshold level andthe input signal crossing a second threshold level at a later time, (v)producing a secondary digital output signal representing the elapsedperiod of time between the input signal crossing a first threshold leveland the input signal crossing a second threshold level at a later time,and (vi) providing a digital representation of the input signal from thesecondary digital output signal and the corresponding primary digitaloutput signal.
 25. The method of claim 24, comprising the further stepsof; providing a single UP/DOWN digital output signal from the primarydigital output signal to indicate in which direction, UP or DOWN, theinput signal crossed the threshold level and providing a digitalrepresentation of the input signal comprising the secondary digitaloutput signals and the associated UP/DOWN digital output signal.
 26. Themethod of claim 25, and further comprising the step of expressing thedigital representation as a 2's complement number.
 27. The method ofclaim 24, and further comprising the step of adjusting the thresholdlevels relative to the input signal in response to a threshold levelcrossing.
 28. The method of claim 24, comprising the step of comparingthe input signal with two threshold levels.
 29. The method of claim 28,comprising the step of adjusting the threshold levels themselves inresponse to the input signal crossing a threshold level so as to adjustthe threshold levels relative to the input signal.
 30. The method ofclaim 31, comprising the step of adjusting the derived signal inresponse to the derived signal crossing a threshold level so as toadjust the threshold levels relative to the derived signal.
 31. Themethod of claim 24, comprising the step of comparing a signal derivedfrom the input signal with the threshold levels.
 32. An analogue todigital converter for converting an analogue input signal into a digitalrepresentation, said converter comprising: generation means forsimultaneously generating a threshold level greater than the currentinput signal and a threshold level less than the current input signal;comparison means for comparing each of the threshold levels with theinput signal and for generating a primary digital output signal toprovide an indication that the input signal has crossed a thresholdlevel; adjustment means for adjusting the threshold levels relative tothe input signal in response to a threshold level crossing so as toensure that, following adjustment one threshold level is greater thanthe input signal at the point of threshold crossing and one thresholdlevel is less than the input signal at the point of threshold crossing;and timing means for determining any elapsed period of time between theinput signal crossing a first threshold level and the input signalcrossing a second threshold level at a later time and for providing asecondary digital output signal representing the elapsed period of time,wherein the secondary digital output signal and the correspondingprimary digital output signal provide a digital representation of theanalogue input signal.
 33. An apparatus for converting an analogue inputsignal into a digital representation, said apparatus comprising:generation means for simultaneously generating a plurality of differentthreshold levels across the expected amplitude range of the inputsignal, for comparison with the input signal; comparison means forcomparing each of the threshold levels with the input signal and forgenerating a primary digital output signal to provide an indication thatthe input signal has crossed a threshold level; and timing means fordetermining the elapsed period of time between the input signal crossinga first threshold level and the input signal crossing a second thresholdlevel at a later time and for providing a secondary digital outputsignal representing the elapsed period of time, wherein the secondarydigital output signal and the corresponding primary digital outputprovide a digital representation of the analogue input signal.